The drive to minimize power consumption is leading to a rapid increase in the number of clocks in today's designs. This is leading to the introduction of design bugs that result in synchronization failures that are extremely hard to identify using simulation alone. Veda's initial product offering is an easy to set-up and use Clock Domain Crossing functional analysis tool called Veda CDC.

Veda CDC quickly elaborates design hardware descriptions (in HDL such as SystemVerilog)  and employs rapid abstraction and structural analysis techniques to automatically identify clocks and clock domains together with data crossings that benefit from  multi-mode functional analysis to determine their safety accurately. Veda CDC can also read in design/clock constraints in SDC format. Veda's comprehensive functional analysis technique involves a semi-formal state space exploration that is much faster and easier to use than traditional exhaustive formal analysis.

Veda CDC can rapidly analyze all the commonly used synchronization techniques such as double and triple registering, recirculating control mux, FIFO/memory based synchronization techniques and the use of Grey codes. Veda's functional analysis can quickly analyze finite state machine control of crossings and validate feedback control structures.

Veda offers both flat and multi-threaded hierarchical CDC analysis as well as an ensemble based machine learning approach to CDC classification.

Veda CDC has a Qt graphical user interface (GUI) that is available on both Linux and Windows platforms. The GUI allows viewing, filtering and editing of the generated SQL data-base of CDC information.

To evaluate Veda CDC, contact us by filling out the Contact Form.